Embodiments of the present invention relate to ramp based clock synchronization for stackable power supply circuits.
Multiple phase stackable power supply circuits are used to generate relatively high currents for various applications such as computers, servers, communications systems, smart power systems, LED lighting systems, and various other applications. Each stackable power supply circuit may be an AC-to-DC or DC-to-DC converter such as a buck converter or buck boost converter. Each stackable power supply circuit is typically connected to a common input bus and a common output bus. They are normally configured as a Master and one or more Slave circuits, each having a respective phase and operating in synchronization with a synchronization clock signal. There are several problems associated with clock synchronization. Referring to FIGS. 1A and 1B, synchronization clocks 102 and 104 must run at a much higher frequency than their respective Master or Slave clocks. The synchronization clocks are frequency divided to produce the Master and Slave clocks in their proper phases. The high frequency synchronization increases system noise, power consumption, and complicates printed circuit board design.
A second problem is that each synchronization clock must include a marker to identify the beginning of each sequence of synchronization clock cycles. For example, FIG. 1A omits a pulse at position 100 to indicate the beginning of a sequence of clock cycles. For a two phase system, the Master clock is then generated at the missing pulse and the Slave clock is generated at the fourth synchronization clock pulse after the missing pulse. The synchronization clock of FIG. 1B uses a relatively higher pulse voltage at position 106 to indicate the beginning of a sequence of clock cycles. Master and Slave clocks then derive their respective phase with reference to pulse 106. This, however, complicates Master, Slave, and synchronization clock design.
In view of the foregoing problems, embodiments of the present invention are directed to generating simplified and more flexible Master and Slave clocks suitable for stackable power supply circuits.